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[ ak4205 ] 016012367 - e - 00 201 6/12 - 1 - 1. general description the ak4205 is a stereo headphone ampli f ier corresponding to high resolution with built - in analog switch for hi - fi m obile . the ak4205 a chieve s industry s leading level ultra - low noise and ultra - low distortion charac teristics (thd+n = - 1 18 db). the ak4205 is available in a small 36 - pin qfn package . it can save the mounting area of the board b y including resistors for gain adjustment and low - pass filter . application: ? ? ? ? 2. features 1. hea d phone a mplifier ? ? ? ? ? , 34 mw thd+n - 1 20 db @600 , 6.7 mw 2. analog switch ? ? , 3 4 mw ? ? ? ? ? ? ? ? ? ? ? ? ak4205 ultra low noise and distortion headphone amp with analog switch
[ ak4205 ] 016012367 - e - 00 201 6/12 - 2 - 3. table of contents 1. general description ................................ ................................ ................................ ............................. 1 2. features ................................ ................................ ................................ ................................ ............... 1 3. table of contents ................................ ................................ ................................ ................................ . 2 4. block diagram ................................ ................................ ................................ ................................ ..... 3 5. pin configurations and functions ................................ ................................ ................................ ....... 4 pin configurations ................................ ................................ ................................ ............................. 4 pin functions ................................ ................................ ................................ ................................ ..... 5 6. absolute maximum ratings ................................ ................................ ................................ ................. 6 7. recommended operating conditions ................................ ................................ ................................ . 7 8. electrical characteristics ................................ ................................ ................................ ..................... 8 analog characteristics ................................ ................................ ................................ ...................... 8 dc characteristics ................................ ................................ ................................ ........................... 11 switching characteristics ................................ ................................ ................................ ................. 11 headphone - amp power - up/down timing ................................ ................................ ........................ 11 timing diagram ................................ ................................ ................................ ............................... 12 9. functional descriptions ................................ ................................ ................................ ..................... 13 9.1 system reset ................................ ................................ ................................ ................................ . 13 9.2 charge pump circuit ................................ ................................ ................................ ...................... 13 9.3 analog switch & mute circuits ................................ ................................ ................................ ....... 14 9.4 headphone amplifier ................................ ................................ ................................ ...................... 15 9.5 control sequence ................................ ................................ ................................ ........................... 16 analog switch power - up/down sequence ................................ ................................ ...................... 16 hi - fi mode ? aux mode pop noiseless change sequence ................................ ...................... 18 10. recommended external circuits ................................ ................................ ................................ ... 19 10.1. general example of external circuit ................................ ................................ ........................... 19 10.2 example of the connection with ak4492 ................................ ................................ ...................... 21 11. example of layout ................................ ................................ ................................ ......................... 22 12. package ................................ ................................ ................................ ................................ ......... 23 outline dimensions ................................ ................................ ................................ ......................... 23 material & lead finish ................................ ................................ ................................ ...................... 23 marking ................................ ................................ ................................ ................................ ............ 23 13. ordering guide ................................ ................................ ................................ ............................... 24 ordering guide ................................ ................................ ................................ ................................ 24 14. revision history ................................ ................................ ................................ ............................. 24 important notice ................................ ................................ ................................ .............................. 25
[ ak4205 ] 016012367 - e - 00 201 6/12 - 3 - 4. block diagram figure 1 . block diagram dac a ch pvdd a swvdd swvss s wout a s wout b nin a pin a avss a rvss c apss bg , vref , iref n in b p in b avss b rstn rvdd pv ee a p vdd b pvee b sel bg charge pump hifi - 3.3v ldo ldo ldo ldo 7 00 (typ) 74 0 (typ) 74 0 (typ) 7 00 (typ) aux a aux b ampo ut b swin b swin a ampout a mute n swvss swvss analog switch charge pump charge pump +6.6v aux - 3.3v 7 00 (typ) 74 0 (typ) 74 0 (typ) 7 00 (typ) dac b ch headphone b ch headphone a ch
[ ak4205 ] 016012367 - e - 00 201 6/12 - 4 - 5. pin configurations and functions pin configurations figure 2 . pin configurations a ux a swin a nc nc pvdd a ampout a muten pvee a swout a nc nc capss swvdd swvss s wout b nin a pin a avss a nc rvdd rvss avss b pin b swin b nc nc pvdd b ampout b pvee b nc nc a k4205 top view 27 26 25 17 16 15 14 13 12 11 10 24 23 22 21 20 1 2 3 4 5 6 7 8 19 aux b 18 nin b 9 sel nc rstn 28 29 30 31 32 33 34 35 36
[ ak4205 ] 016012367 - e - 00 201 6/12 - 5 - pin functions no. pin name i/o function 1 nina i negative analog input a pin 2 p in a i positive analog input a pin 3 avssa - analog ground a pin 4 nc - no connect pin. this pin should be connected to vss. 5 rvdd - reference power supply, 4.5 ~ 6 .5 v 6 rvss - reference ground pin 7 avssb - analog ground b pin 8 pinb i positive analog input b pin 9 ninb i negative analog input b pin 10 nc - no connect pin. this pin should be connected to vss. 11 nc - no connect pin. this pin should be connected to vss. 12 pveeb - headphone amp negative power supply b pin, - 4.5 ~ - 5 .5 v 13 ampoutb o headphone amp output b pin 14 pvddb - headphone amp positive power supply b pin, 4.5 ~ 6 .5 v 15 nc - no connect pin. this pin should be connected to vss. 16 nc - no connect pin. this pin should be connected to vss. 17 swinb i hifi path switch input b pin 18 auxb i aux path switch input b pin 19 swoutb o switch output b pin 20 nc - no connect pin. this pin should be connected to vss. 21 sel i hifi/aux path select pin h : hifi pa th ( swina/b pins), l : aux path (auxa/b pins) 22 swvss - switch ground pin 23 swvdd - switch power supply pin, 3.0 ~ 3.6 v 24 capss o soft start capacitor terminal pin 25 nc - no connect pin. this pin should be connected to vss. 26 nc - no connect pin. this pin should be connected to vss. 27 swouta o switch output a pin 28 auxa i aux path switch input a pin 29 swina i hi - fi path switch input a pin 30 nc - no connect pin. this pin should be connected to vss. 31 nc - no connect pin. this pin should be connected to vss. 32 pvdda - headphone - amp positive power supply a pin, 4.5 ~ 6 .5 v 33 ampouta o headphone - amp output a pin 34 pveea - headphone - amp negative power supply a pin, - 4.5 ~ - 5 .5 v 35 rst n i reset pin when l, the ak4 205 is held in reset. the ak 4205 must be always reset upon power - up. 36 muten i mute control pin h : normal operation l : swouta and swoutb pins are mute state. exposed pad - the exposed pad on the bottom surface of the package should be connected to vss. ( note 2 ) note 1 . all digital input pins (sel, rstn, muten pins) expect analog input/output pins ( nina, pina, pinb, ninb, swinb, auxb, auxa, swina ) should not be left floating. i/o pins should be processed appropriately . note 2 . exposed pad is not connected to vss internally.
[ ak4205 ] 016012367 - e - 00 201 6/12 - 6 - 6. a bsolute m aximum r atings ( a vss a = avss b =rvss=swvss= 0v; note 3 ) p ar ameter symbol m in . m ax . unit power supplies headphone positive rvdd pvdda pvddb ? ? ? ? ? ? ? ? ? ? ? ? ? ? must be connected to the same analog ground plane. rvdd / pvdda / pvddb and pveea / pveeb must be connected to the same analog power supplies each . note 4 . except rvdd, pvdda , pvddb, swvdd, swina , swinb , auxa and auxb pins note 5 . swina, swinb , auxa and auxb pins note 6 . pina, nina, pinb and ninb pins note 7 . the maximum value of vina1 is (rvdd+0.3)v or 7.0v , whichever is lower . note 8 . swina, swinb, auxa and auxb pins at on state note 9 . the maximum value of vina2, vina3 and vind is (swvdd+0.3)v or 4.0v , whichever is lower . note 10 . swina, swinb, auxa and auxb pins at off state note 11 . rstn , sel, muten pins note 12 . this value is the internal loss of the ak4205, excluding the consumption of external dumping resistance and headphone. the maximum allowable junction temperature of the ak4205 is 125 ? c . the ja (junction to ambient ) in jesd51 - 9(2p2s) is 39.6 ? c /w , and the internal temperature rise is 0.5w 39.6 = 19.8 ? c . warning : operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes.
[ ak4205 ] 016012367 - e - 00 201 6/12 - 7 - 7. r ecommended o perating c onditions ( a vss a = avss b =rvss=swvss= 0v; note 13 ) p ar ameter symbol m in . t yp . m ax . unit power supplies ( note 14 ) headphone positive rvdd pvdda pvddb 4.5 6.0 6.5 v headphone negative pveea pveeb - 5.5 - 5.0 - 4.5 v switch sw vdd 3.0 3.3 3.6 v damping resistor rd - 33 - pvdd a 0.1 - - pvdd b 0.1 - - pvee a 0.1 - - pvee r 0.1 - - dc1 - 2.5 - v ( note 17 ) v dc2 - 0 - v ( note 18 ) v dc3 - 0.3 0 0.3 v load resistance rl 16 - - in particular, in order to avoid output pop noise, turn on the power supply of rvdd, pvdda, pv ddb, pveea and pveeb after swvdd is completely powered up . when swvdd = on, rvdd, pvdda, pvddb, pveea and pveeb can be turned off. refer to analog s witch power - up/down sequence about power up/down sequence of each power suppl y . note 15 . place them as close as possible to the ic. refer to example of layout about detail. note 16 . pina, nina, pin b and ninb pins note 17 . swin a , swin b , aux a and aux b pins at on state note 18 . swin a , swin b , aux a and aux b pins at off state warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ ak4205 ] 016012367 - e - 00 201 6/12 - 8 - 8. electrical characteristics analog characteristics (ta = 25 ? c; pvdda = pvddb = rvdd = 6.0 v, pveea = pveeb = - 5.0 v, swvdd = 3.3 v ; avssa = avssb = rvss = swvss = 0 v; signal frequency , level =1 khz , 2 vrms; meas urement bandwidth = 20 hz ? 20 khz ; unless otherwise specified) p ar ameter m in . t yp . m ax . unit hp - amp + analog switch : pin a - nin a , pin b - nin b pins (full differential input) ampou pins swin pins swout , rd=33 ( ? ? note 21 . measured by audio precision apx555 . note 22 . a value of ic itself, the ak4205. it does not include the noise of measuring instrument . note 23 . measured by audio precision sys 2722. figure 3 . measurement circuit for hp - amp + analog switch swout a pin (swout b pin) nin a pin (nin b pin) pin a pin (pin b pin) avss a pin (avss b pin) swin a pin (swin b pin) a mpouta pin (ampout b pin) rl rd sel pin = h dc 2.5 v dc 2.5 v
[ ak4205 ] 016012367 - e - 00 201 6/12 - 9 - p ar ameter m in . t yp . m ax . unit hp - amp block : pina - nina, pinb - ninb pins (full differential input) note 25 . a value of ic itself, the ak4205 . it does not include the noise of measuring instrument . note 26 . measured by a u dio precision sys 2722 . note 27 . input signal is dc2.5 v note 28 . when sine wave of 500 mvpp is superimposed on pvdda, pvddb, pveea, pveeb. note 29 . for analog characteristics of the headphone amplifier that is not listed in the above column, refer to the analog characteristics of the headphone amplifier + analog switch par t. note 30 . when only using the headphone amplifie r , the power supply voltage described in the recommended operating conditions should also be input to swvdd figure 4 . measurement circuit for headphone - amp nin a pin (nin b pin) pin a pin (pin b pin) avss a pin (avss b pin) ampout a pin (ampout b pin) rl rd dc 2.5 v dc 2.5 v
[ ak4205 ] 016012367 - e - 00 201 6/12 - 10 - p ar ameter min. typ. max. unit analog switch block : swin a , swin b pins (single - ended input) or aux a , aux b pins (single - ended input) swout ) ) (sel pin = h) (sel pin = l) . ) the specification is shown in f igure6. note 32 . psrr is applied to swvdd with 500mvpp sine wave . hi - fi mode (sel pin = h) aux mode (sel pin = l) figure 5 . measurement circuit for analog switch aux hi - fi (sel pin = h) hi - fi aux (sel pin = l) figure 6 . measurement circuit for off isolation p ar ameter m in . t yp . m ax . unit power suppl y current : power up (all circuit power up) pvdda + pvddb ( quiescent, iout = 0a ) - 5.4 11.5 ma pveea+pveeb ( quiescent, iout = 0a ) - 6.5 13.0 ma rvdd - 2.0 3.0 ma swvdd rstn pin = rstn pin = a swout a pin (swout b pin) swin a pin (swin b pin) rl aux a pin (aux b pin) open sel pin = h dc 0v swout a pin (swoutb pin) swin a pin (swin b pin) rl aux a pin (aux b pin) open sel pin = l dc 0v swout a pin (swout b pin) swin a pin (swin b pin) rl =32 aux a pin (aux b pin) open sel pin = h 2.0vpp dc 0v swout a pin (swout b pin) swin a pin (swin b pin) rl =32 aux a pin (aux b pin) open sel pin = l 2.0vpp dc 0v
[ ak4205 ] 016012367 - e - 00 201 6/12 - 11 - dc characteristics (ta = - 40 ~ 8 5 ? c; pvdda = pvddb = rvdd = 4.5 v ~ 6.5 v, pveea = pveeb = - 4.5 v ~ - 5.5 v, swvdd = 3.0 v ~ 3.6 v ; avssa = avssb = rvss = swvss = 0 v) p ar ameter symbol m in . t yp . m ax . unit sel, muten, rstn pins high - level input voltage vih 1.44 - - v low - level input voltage vil - - 0.36 v input rising time tr 20 ns input falling time tf 20 ns input leakage current iin - - 0.5 a switching characteristics (ta = - 40 ~ 8 5 ? c; pvdda = pvddb = rvdd = 4.5 v ~ 6.5 v, pveea = pveeb = - 4.5 v ~ - 5.5 v, swvdd = 3.0 v ~ 3.6 v ; avssa = avssb = rvss = swvss = 0 v) p ar ameter ( figure 7 ) symbol m in . t yp . m ax . unit soft start timing ( rl=32 css=0.1 f: note 33 ) turn - on time ton 5 9 ms turn - off time toff 2 9 ms turn - on slope (vin = 20 mv) tslon 1.0 v/s turn - off slope (offset vin = 20 mv) tsloff 1.0 v/s reset timing (rstn pin: note 33 ) rstn pulse width (css = 0.1 headphone - amp power - up/down timing p ar ameter ( figure 9 ) symbol m in . t yp . m ax . unit vdd power up slope ( note 34 ) pusldd - - 15 mv/ s vee power up slope ( note 35 ) puslee - 50 - - mv/ s vdd power down slope ( note 34 , note 36 ) pdsldd - 100 - - mv/ s vee power down slope ( note 35 , note 36 ) pdslee - - 260 mv/ s vdd - vee non - overlap time tpu 0 - - ms vee - vdd non - overlap time tpd 0 - - ms note 34 . rvdd, pvdda, pvddb pins note 35 . pveea, pveeb pins note 36 . at power down, set the absolute value of the vol tage s of rvdd, pvdda and pvddb so that they do not fall below the absolute value of the voltage of pveea and pveeb .
[ ak4205 ] 016012367 - e - 00 201 6/12 - 12 - timing diagram figure 7 . soft transition timing figure 8 . reset timing figure 9 . headphone - amp power - up/down timing t rst vil 1 rstn p veea pvee b rvdd pvdda pvdd b 0v 70% vdd 0v tpu tpd vdd vee pusldd p dsldd p uslee p d sl ee swout a pin (swout b pin) swin a pin (swin b pin) rl =32 aux a pin (aux b pin) vin,dc sel pin = l h open vout
[ ak4205 ] 016012367 - e - 00 201 6/12 - 13 - 9. functional descriptio n s 9.1 system reset power supplies must be applied when the rst n pin = l . set the rstn pin to h to release power - down after lapse of 1 ms or longer from swvdd power - up . the charge pump circuit starts to operate after the rstn pin is set to h , and then the positive and negative voltage for analog switch are generated . 9.2 charge p ump circuit the positive and negative power s are generated by built - in charge pump circuit from swvdd voltage when rstn pin = h . the se generated powers are used for the analog switch. i nput and output signals for the analog switch are single - ended and centered around on vss (0v). the ak4205 has built - in capacitors for charge pump circui t ; therefore no external capacitors are necessary. the power - up time of the charge pump circuit is typ. 100 s (max. 500 s ). the operating frequency of the charge pump circuit is depended on internal oscill ator (typ. 4.5mhz). rvdd, pvdda/b and pveea/b must be supplied after power - up the charge pump circuit. figure 10 . charge pump circuit swvdd pin swvss pin swout a pin s woutb pin bg charge pump hi - fi - 3.3v aux a pin aux b pin swin b pin swin a pin swvss swvss analog switch charge pump charge pump +6.6v aux - 3.3v 0v 0v 0v 0v +3.3v headphone headphone
[ ak4205 ] 016012367 - e - 00 201 6/12 - 14 - 9.3 analog switch & mute circuits the ak4205 has an analog switch circuit with ultra - low on - resistance. it is able to a chieve a 124 db s/n (a - weighted) and - 118db thd+n when combined with a headphone amplifier that has u ltra - low noise and distortion . when the muten pin = h and the sel pin = l , the signals input to the auxa and auxb pin s are output from the swouta and swoutb pin s , respectively . at this time, the swina and swinb pins are pulled down to swvss by 4 (typ) resist ance of swa and swb switches . when the muten pin = h and the sel pin = h , input signals to the swina and swinb pin s are output from the swouta and swoutb pin s , respectively . soft mute transition is executed when changing the path (sel pin = l h or h l ) or when releasing a mute (muten pin = l h ) to reduce pop noises . these transition times depend on the time constant of a capacitor that is connected to the capss pin. turn - off time will be 29ms (typ.) and turn - on time will be 59ms (typ.) if the capacitor value css = 0.1 f setting of the sel pin is ignored and the swouta and the swoutb pins become mute state immediately by setting the muten pin to l . table 1 . modes control (x: do not c ar e) muten pin sel pin mode l x mute state ( swouta/b pins output hi - z) h l aux mode (auxa/b pins are enable d ) h hi - fi mode (swina/b pins are enable d ) aux mode (sel pin = l ) hi - fi mode (sel pin = h ) figure 11 . aux mode and hi - fi - mode sel pin muten pin swout a pin swout b pin aux a pin aux b pi n swin b pin swin a pin swvss swvss analog switch 0v 0v 0v 0v sel pin h l h l s w a s w b h l capss pin 0.1f (css) swout a pin aux a pin aux b pin swin b pin swin a pin swvss swvss analog switch 0v 0v 0v 0v sel pin h l h l s w a s w b sel pin muten pin h h swout b pin capss pin 0.1f (css)
[ ak4205 ] 016012367 - e - 00 201 6/12 - 15 - 9.4 headphone amplifier positive power of the internal headphone amplifier is supplied from the pvdda/b pins and the negative power is supplied from the pveea/b pins. in these condition, ak4492 achieves - 118db thd+n. the headphone outputs (ampouta/b pins) are single - ended outputs centered around vss ( 0 v ) and dc cut capacitors are not necessary . a load resistance is 49 (min.) including damping resistor (rd). the headphone amplifier in puts should be fully differential in puts cantered at 2. 5 v pp dc bias voltage ( pina - nina pins, pinb - ninb pins ). the swouta/b pin can output a 2vrms when the input voltage pinb - nina pins (pinb - ninb pins) = 2 vrms, damping resistance (rd) = 33 and headphone load resistance (rl) = 600 . figure 12 . headphone amplifier swout a pin (swout b pin) nin a pin (nin b pin) pin a pin (pin b pin) avss a pin (avss b pin) swin a pin (swin b pin) ampout a pin (ampout b pin) rl rd sel pin = h dc2.5v dc2.5v
[ ak4205 ] 016012367 - e - 00 201 6/12 - 16 - 9.5 control sequence analog s witch power - up/down sequence figure 13 . power - up/down sequence < power up sequence> (1) power up swvdd while the rstn , sel and muten pins are all l . (2) set the rstn pin l h after power up swvd d. 1 ms or more l period of the rstn pin is necessary for a curtain reset of the ak4205. (3) aux signal output: muten pin l h the analog switch near aux side will be powered on gradually by setting the muten pin to h after 5 ms from the reset release. mute release time is determined by a capacitor connected to the capss pin. for example , it will be 220 ms (typ.) if the capacito r value (css) is 0.1 f. (4) change to hi - fi mode : sel pin l h the data path is switched to hi - fi by setting the sel pin = h after a lapse of 300 ms or more from the muten pin = h . the sel pin should be set to h after stopping the input of the auxa/b pin s . the transition time depend on the time constant of a capacitor that is connected to the capss pin. it will be 220 ms (typ.) if the capacitor value (css) is 0.1 f. c h a nge to aux mode: sel pin h l the data path is switched to aux by setting the sel pin = l . the sel pin should be set to l after stopping the swina/b pins input. the transition time is determined by a capacitor connected to the capss pin. for example , it will be 220 ms (typ.) if the capacitor value (css) is 0.1 f. muten pin sel pin switch state capss pin off auxa/b pin s (1) ( 7 ) ( 5 ) ( 4 ) (6) rstn pin swvdd pin > 1 ms >5ms >1ms >2ms > 300ms off aux 0v aux aux hi - fi hi - fi hi - fi aux aux off ( 2 ) ( 3 ) 2.5v 1.4v ( 8 ) typ. 220ms > 300ms typ. 220ms swina/b pins 0v swouta/b pins 0v > 300ms
[ ak4205 ] 016012367 - e - 00 201 6/12 - 17 - figure 13. power - up/down sequence (5) it is re commended that t he data path is switched to aux by setting the sel pin = l to avoid pop noise in power down sequence. (6) stopping switch output: muten pin h l when the muten pin = "l", swouta / b pins turns off momentarily. in order to avoid pop noise , set the muten pin = "l" after 300 ms or more from the sel pin = "l". (7) after muting the output : rstn pin l h after 1 ms from muting the output, set the rstn pin to l . (8) after 2 ms or more from the rstn pin = "l", turn off swvdd power supply. muten pin sel pin switch state capss pin off auxa/b pin s (1) ( 7 ) ( 5 ) ( 4 ) (6) rstn pin swvdd pin > 1 ms >5ms >1ms >2ms > 300ms off aux 0v aux aux hi - fi hi - fi hi - fi aux aux off ( 2 ) ( 3 ) 2.5v 1.4v ( 8 ) typ. 220ms > 300ms typ. 220ms swina/b pins 0v swouta/b pins 0v > 300ms
[ ak4205 ] 016012367 - e - 00 201 6/12 - 18 - hi - fi mode ? figure 14 . hi - fi ? aux path switching sequence (1) at first, set up analog switch according to the its power - up/down sequence (refer to p16. analog s witch power - up/down sequence (1)~(3) ) . changing aux mode ? (2) when the aux input is 0v, power up headphone - amp power s upplies (rvdd, pvdda/b, pveea/b). after rvdd and pvdda/b are powered up, power up pveea/b. (refer to p11. headphone - amp power - up/down timing ) (3) when the headphone - amp is powered up, power up the power supply of dac connected near hi - fi side. (4) after dac output is enable d : sel pin l h do not input signal to the swina/ b pins in the middle of transition . (5) dac signal starts being output . changing hi - fi mode ? (6) set the sel pin h l after stopping dac output. set the sel pin to l after the dac is muted or data input is stopped. (7) power - up the dac with an interval of 300ms or more after setting the sel pin to l . (8) turn off the headphone amplifier power supplies (pveea/b, rvdd, pvdda/b) after power downing the dac. pveea/b must be powered down before rvdd and pvdda/b. (refer to p11. headphone - amp power - up/down timing ) dac sel pin switch state capss pin auxa/b pin s ( 8 ) ( 6 ) ( 5 ) ( 7 ) pveea/b rvdd, pvdda/b *1 0v aux aux hi - fi hi - fi hi - fi aux aux ( 2 ) ( 3 ) 2.5v > 300ms swina/b pins 0v swouta/b pins 0v 1.4v *1: dac power - up time *2 : dac power - down time ( 4 ) 0v 0v power - up power - down > 300ms 70% > 0ms > 0ms *2 typ. 220ms typ. 220ms dac m ute or no signal i nput muten pin (1) rstn pin swvdd pin >1ms >5ms
[ ak4205 ] 016012367 - e - 00 201 6/12 - 19 - 10. recommended external circuits 10.1. general example of external ci r cuit figure 15 shows the system connection diagram. an evaluation board (akd 4205 ) is available for fast evaluation as well as suggestions for peripheral circuitry. figure 15 . circuit example with ak4205 note: - r vss, sw vss , avssa and avssb of the ak4205 must be distributed separately from the ground of external controllers. - avssa, avssb and headphone ground must be connected to the same analog ground plane to minimize contact impedance . - the capss pin should be connected to the ground with 0. 1 ? f or more capacitor to minimize pop & click noise by switching path . - it is recommended to connect inductors (typ. 470nf) between swouta/b and headphone outputs, and zener diodes (v rwm = 5v) between headphone outputs and the analog ground for a circuit design considering the iex61000 - 4 - 2 standard . swout a nc nc capss swvdd swvss swout b sel nc nc pvee b ampout b pvdd b nc aux b muten rstn pvee a ampout a pvdd a nc nc swin a pin a avss a nc rvdd rvss avss b pin b nin b 36 35 34 26 25 24 23 22 21 20 19 33 32 31 30 29 10 11 12 13 14 15 16 17 28 nin a 27 aux a 18 nc swin b nc 1 2 3 4 5 6 7 8 9 power supply 4.5 ? 6.5 v power supply - 5.5 ? - 4 .5v css= 0 .1u acpu power supply 3.0 ? 3. 6 v analog ground digital ground 33 ak4205 top view headphone a ch headphone b ch aux in ( b ch) aux in ( a ch) dac a ch dac b ch 0.1u 10u 0.1u 10u 0.1u 0.1u 10u 10u 33 1 0 u 1 0 u 0. 1u 0. 1u dc 2.5v dc 2.5v dc 0v dc 0v dc 2.5v dc 2.5v 470n 470n 5v rwm zener diode 5v rwm zener diode
[ ak4205 ] 016012367 - e - 00 201 6/12 - 20 - 1. grounding and power supply decoupling the ak4 205 requires careful attention to power supply and grounding arrangements. pvdda, pvddb, pveea, pveeb and rvdd are usually supplied from the systems analog supply, and sw vdd is supplied from the systems another analog power supply. rvdd / pvdda / pvddb and pveea / pveeb must be connected to the same analog power supplies each . the rst n pin should be held l when power supplies are tuning on. the rst n pin is allowed to be h after swvdd is applied and settled. in order to avoid the pop noise of swouta and swoutb output at power - up/down, refer to p16. analog s witch power - up/down sequence r vss, sw vss , avssa, avssb and expose pad of the ak4 205 should be connected to the analog ground plane. system analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. decoupling capacitors should b e as close the power supply pins as possible. especially, the small value bypass capacitor is to be closest. 2 . analog inputs the headphone amplifier input s (pina - nina pins and pinb - ninb pins) support full - differential format. t he input signal range i s nominally typ. 2.83 vpp , centered around 2 .5 v. the analog switch input s (swina, swinb, auxa and auxb pins) support single - ended format. t he input signal range i s nominally typ. 6.0 vpp, centered around vss (0 v ) . 3 . analog outputs the headphone output (ampouta and ampoutb pin s) is single - ended and centered around vss (0 v). there is no need for ac coupling capacitors. the ampouta and ampoutb pin s should be connected to swina and swinb pins with a dumping resistor (rd) in series. the analog switch output (swouta and swoutb pins ) is single - ended and centered around vss (0 v) , and they should be connected directly to a headphone . there is no need for ac coupling capacitors.
[ ak4205 ] 016012367 - e - 00 201 6/12 - 21 - 10.2 example of the connection with ak4492 the ak4492 is a 32 - bit 2ch premium dac. ultra low distortion characteristics are realized by distortion reduction technology. the digital input supports up to 768 khz pcm and 11.2 mhz dsd (direct stream digital), making the ak4205 suitable for high - resolution sound sour ce playback that is becoming popular with smart phones, audio players and etc . a connection example with the ak4492 is shown below. vss and dvss should not interfere each other by the layout design . figure 16 . circuit example with ak4205 and ak4492 power supply 6 v power supply - 5v css= 0.1u rd 33 a k4205 top view headphone r ch headphone l ch aux in (b ch) aux in (a ch) 0.1u 10u 0.1u 10u 0.1u 0.1u 10u 10u rd 33 1 0 u 1 0 u 0. 1u 0. 1u dc 2.5v dc 2.5v dc 2.5v dc 2.5v d vss 0v dvdd 1.8v vss dvss 0.1 ? f vss 0v bick sdata lrck mcl k b ick/bck/dclk(j1 ) s data/dinl/dsdl(h1 ) lrck/dinr/dsdr( g1 ) s low/cdti/sda(e1 ) d vss(k2 ) t vdd(j2 ) d if2/cad0(d2 ) h load/i2c(c2 ) a cks/cad1(a2 ) d vdd(k3 ) l doe(h 3 ) p sn(d3) t dm1(b3 ) a vdd(k4 ) a vss(j4 ) d chain(b4 ) i nvr(a4 ) a k4492 s mute/csn(f1 ) mclk( j3 ) t este(b5 ) a outrp(b 9) a outrn(a9 ) v ssr(d10,e9,e10 ) v ddr(c9 , c10 , d9 ) vrefhl( k5 , k6 ) v refll(l7,k8 ) v cml(j8 ) aoutln( k9 ) aoutlp(j 9 ) v ddl(g9,h9,h10 ) v ssl(f9,f10,g10 ) v cmr(b8 ) vreflr( a7,a8 ) v refhr(a5 , a6 ) d if0/dzfl(d1 ) s slow/wck(g2 ) t dmo(f2 ) gain/dsdr(b 2 ) t dm0/dclk(a3 ) e xtr(j5 ) 0.1 ? f 0.1 ? f 1 ? f s d/cclk/scl( e2 ) p dn(h2 ) d if1/dzfr(c1 ) d em0/dsdl(b1 ) 51ohm 33kohm 1 ? f 1 ? f 1 ? f vdd 5v acpu 1 ? f swvdd 3.3v e x ternal regulator circuit swout a nc nc capss swvdd swvss swout b sel nc nc pvee b ampout b pvdd b nc aux b muten rstn pvee a ampout a pvdd a nc nc swin a pin a avssa nc rvdd rvss avss b pin b nin b 36 35 34 26 25 24 23 22 21 20 19 33 32 31 30 29 10 11 12 13 14 15 16 17 28 nin a 27 aux a 18 nc swin b nc 1 2 3 4 5 6 7 8 9 tab nc a k4205 e xternal regulator circuit 470n 470n 5v rwm zener diode 5v rwm zener diode
[ ak4205 ] 016012367 - e - 00 201 6/12 - 22 - 11. example of layout figure 17 shows the recommended layout of the ak4205. figure 17 . recommended l ayout example of ak4205 note: - c onnect avssa, avssb, rvss, swvss and exposed pad (tab) on the reverse side of the ic at the top layer and minimize the wiring impedance between each pin as much as possible. when connected with via, the characteristics such as thd may deteriorate due to parasitic inductance. - place the bypass capacitor between pvdda, pvddb, pveea, pveeb and gnd in the immediate vicinity of the ic and minimize the wiring impedance as much as possible. - for circuit design considering the iec 61000 - 4 - 2 standard, it is recommended to co nnect an inductor (typ . 470 nf) between the swouta / b terminal and the headphone output , and a zener diode (v rwm = 5 v) between the headphon e output and the analog ground .
[ ak4205 ] 016012367 - e - 00 201 6/12 - 23 - 12. package outline dimensions * the exposed pad on the bottom surface of the package must be connected to the ground. material & lead finish package molding compound: epoxy resin, halogen (br and cl) free lead frame material: cu alloy pin surface treatment: solder (pb free) plate (sn100 %) marking x xxxx: date code (5 digit s ) pin #1 indication ak4205 xxxx x 1 akm
[ ak4205 ] 016012367 - e - 00 201 6/12 - 24 - 13. o r dering guide ordering guide ak4205 en - 40 ~ +85 c 36 - pin qfn 14. revision history date (y/m/d) revision reason page contents 1 6 / 12 / 22 00 first edition
[ ak4205 ] 016012367 - e - 00 201 6/12 - 25 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make in quiries the sales office of akm or authorized distributor s as to current status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may c ause loss of human life, bodily injury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, train s, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use produ ct for the above use unless specifically agreed by akm in writing . 3. though akm works continually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards f or your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherw ise make available the product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological w eapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5 . please contact akm sales representative for details as to environmental matters such as the rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the stateme nt and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

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